1. Field of the Invention
The invention relates to a method for fabricating shallow trench isolation (STI) structure.
2. Description of the Prior Art
Generally, shallow trench isolations (STIs) are used to separate and isolate active areas on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches, overfilling the trenches with a dielectric such as an oxide, and then removing any excess dielectric with a process such as chemical mechanical polishing (CMP) or etching in order to remove the dielectric outside the trenches. This dielectric helps to electrically isolate the active areas from each other.
However, conventional means for fabricating STIs typically utilizes a flowable chemical vapor deposition (FCVD) or spin-on-dielectric (SOD) process to refill the trench with an oxide layer. As these processes have serious silicon consumption issues, an alternative approach of forming a stress buffer film (SBF) or amorphous silicon layer in the trench before filling of oxide layer has been derived. Nevertheless, the utilization of the SBF or amorphous layer also raises additional issues as the remaining of these layers while not being fully consumed, often results in bending of fin-shaped structures.